[Slightly Revised 1/20/2019]

1. Set VDIMM and VSOC to baseline values.
2. Set frequency to a baseline value.
3. Primary timings: initial tightening and gauging baseline timings

1. tCL, tRCD, tRP

1. Set tCL, tRCD, tRP, tRAS somewhat loose.

1. Unstable: Repeat until stable:

1. tCL + 1, tRCD + 1, tRP + 1, tRAS + 2

2. Repeat until decrease of either pair causes instability:

1. tCL - 1, tRP - 1

1. Record subtimings.
2. Stress test.

2. tRCDWR - 1, tRCDRD - 1

1. Stress test.

3. Repeat until stable:

1. tRP - 1

1. Stress test.

2. tRAS

1. Set to the lower of the following values, if lower than current value:

1. Values recommended by DRAM Calculator.
2. tRAS = tCL + tRP or tCL + tRP + 2

2. Stress test.

1. Unstable: repeat until stable:

1. tRAS + 2

1. Stress test.

2. Stable: repeat until unstable:

1. tRAS - 2

1. Stress test.

4. Repeat at higher frequencies until true CAS latency required for stability is relatively very high.

1. Increase VDIMM and VSOC if necessary.
2. Determine frequency/-ies at which best true latency was achieved or which may achieve best true latency after more tweaking.
3. Repeat until either one causes instability or calculator minimum voltages reached, whichever is higher:

1. VDIMM - 1 step.
2. VSOC - 1 step.

5. Process for the following sections:

1. Unstable (boot cycle): clear CMOS.
2. Unstable (training failed): do the following, in order, until training successful:

1. Change ProcODT.
2. Change RTT_PARK.
3. (If safe) VDIMM + 1 step, then repeat.
4. (If safe) VSOC + 1 step.
5. (If safe) Vcore + 1 step, then repeat.

3. Unstable (BSOD/crash): do the following, in order, until stable:

1. ProcODT ± 1 step, then repeat.
2. (If safe) VDIMM + 1 step, then repeat.
3. (If safe) VSOC + 1 step.
4. (If safe) Vcore + 1 step, then repeat.
5. Nothing worked: change CLDO_VDDP and disable Spread Spectrum.

4. Stable (boots): stress test.
5. Unstable (memory errors): do the following, when applicable/safe/possible, in order, until stable:

1. Change CAD_BUS, then repeat.
2. Change VDDP, then repeat.
3. Change memory interleaving.
4. Vcore + 1 step, then repeat.
5. VDIMM + 1 step, then repeat.
6. (Maybe VSOC + 1 step?)
7. VSOC LLC + 1, then repeat.
8. Set Geardown enabled (NOTE: THIS MAKES MANY TIMINGS ROUND UP IF THEY ARE ODD).
9. Disable Spread Spectrum.
10. Change timings:

1. Set and loosen timings: tFAW (keep between 16 and 36), tRDWR (between 6 and 9), tWRRD (between 1 and 4), tRCDRD
2. tRRDS + 1 or + 2
3. Set tRFC to alternative calculator value.
4. tRP ± 1

11. Nothing worked: change:

1. CLDO_VDDP (for memory holes), VPP, PLL voltage
2. Loosen timings (and disable Geardown if loosening tCL)

6. Primary timings: further tightening

1. Where possible, set values for the following: RTT_PARK, RTT_NOM, RTT_WR, ProcODT, CAD_BUS (CLKDrvStr/AddrCmdDrvStr/CsOdtDrvStr/CKEDrvStr), VDDP, CLDO_VDDP, VPP, PLL Voltage.
2. Repeat, in order, doing as many as of the following as possible until unstable:

1. tCL - 1

1. See 5.

2. (If tRP did not need to be loosened previously) tRP - 1

1. See 5.

3. tRCDWR - 1

1. See 5.

4. (If tRCDRD did not need to be loosened previously) tRCDRD - 1

1. See 5.

3. Repeat until unstable

1. tRAS - 2

1. See 5.

7. Subtimings

1. Set to values recommended by DRAM Calculator, if lower than current values.

1. See 5.

2. tRC

1. Set tRC = tRP + tRAS.

1. Stress test.

2. Unstable: repeat until stable:

1. tRC + 2
2. Stress test.

3. tRFC

1. If lower than recommended value, set tRFC = 8(tRC) + 8.

1. Stress test.

2. Repeat until opposite state of stability is reached:

1. Unstable: tRFC + 32; Stable: tRFC - 32.

1. Stress test.

3. Stable: tRFC - 16; Unstable: tRFC + 16.

1. Stress test.
2. Unstable: tRFC + 8; Stable: tRFC - 8.

1. Stress test.
2. Stable: tRFC - 4; Unstable: tRFC + 2.

1. Stress test.
2. Unstable: tRFC + 2; Stable: tRFC - 2.

1. Stress test.
2. Stable: tRFC - 1; Unstable: tRFC + 1.

1. Stress test.

4. tCKE

1. Repeat until unstable:

1. tCKE - 1
2. Stress test.

5. tCWL

1. If lower than recommended value, set tCWL = tCL or tCWL = tCL - 1 (whichever is even).

1. Stress test.

2. Repeat until unstable:

1. tCWL - 1
2. Stress test.

6. tRRDS, tRRDL

1. Repeat until reducing either one causes instability:

1. tRRDS - 1

1. Stress test.

2. tRRDL - 1

1. Stress test.

7. tRDRDSCL, tWRWRSCL

1. Repeat until reducing either one causes instability:

1. tRDRDSCL - 1

1. Stress test.

2. tWRWRSCL - 1

1. Stress test.

8. (If greater than 1) tWRWRSC, tRDRDSC

1. Repeat until reducing either one causes instability:

1. tWRWRSC - 1

1. Stress test.

2. tRDRDSC - 1

1. Stress test.

9. tWRWRDD, tWRWRSD

1. Repeat until reducing either one causes instability:

1. tWRWRSD - 1

1. Stress test.

2. tRDRDSD - 1

1. Stress test.

10. tRDRDSD, tRDRDDD

1. Repeat until reducing either one causes instability:

1. tRDRDSD - 1

1. Stress test.

2. tRDRDDD - 1

1. Stress test.

11. tFAW (If tFAW did not need to be loosened previously)

1. Set to 4(tRRDS).
2. Unstable: Set to 5(tRRDS).

1. Unstable: Set to 8(tRRDS).

1. Unstable: Repeat until stable:

1. tFAW + 2.
2. Stress test.

2. Stable: Repeat until unstable:

1. tFAW - 2.
2. Stress test.

2. Stable: Repeat until unstable:

1. tFAW - 2.
2. Stress test.

12. tWTRS (If tWTRS did not need to be loosened previously), tWTRL

1. Repeat until reducing either one causes instability:

1. tWTRS - 1

1. Stress test.

2. tWTRL - 1

1. Stress test.

13. tWR

1. If lower than recommended value, set tWR = tRAS - tRCD
2. Repeat until unstable or tWR = 8:

1. tWR - 1
2. Stress test.

14. tRTP

1. Repeat until unstable:

1. tRTP - 1
2. Stress test.

15. tRDWR (If tRDWR did not need to be loosened previously), tWRRD (If tWRRD did not need to be loosened previously)

1. Repeat until reducing either one causes instability:

1. tRDWR - 1
2. tWRRD - 1

16. CR (If 2)

1. CR - 1
2. DISABLE GEARDOWN MODE
3. Stress test.

8. Repeat until either one causes instability:

1. VDIMM - 1 step.
2. VSOC - 1 step.